1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same, and more particularly, to a vertical MOS transistor wherein the effects of a parasitic bipolar transistor are reduced and a method therefor.
2. Description of the Related Art
FIG. 1 shows a cross-sectional view of a conventional vertical MOS FET.
As shown in FIG. 1, an n.sup.- epitaxial layer 12 is formed, as a drain region, on a semiconductor substrate 10, and a well-shaped p.sup.+ region 14 is formed on the n.sup.- epitaxial layer 12. A square shaped n.sup.+ region 16 is formed in the p.sup.+ region 14, as a source region and gate electrodes 18 having a square shape are formed on a gate oxide film 20 on the p.sup.+ region 14.
Then a source electrode 22 is formed inside the gate electrode 18 so that it is brought into contact with a source region 16.
The source electrode 22 and the gate electrode 18 are insulated by a PSG film 24, and a drain electrode 26 is formed on a back side of the semiconductor substrate 10.
When the resistance R in the p.sup.+ region 14 under the source region 16 is large in the vertical MOS FET, a parasitic bipolar transistor is generated around the channel region of the vertical MOS FET during a high voltage operation, and thus the MOS FET is destroyed.
Namely, when a junction between a n.sup.- region 12 and a p.sup.+ region 14 is broken down during a high voltage operation, a voltage of a resistance R due to a break down current occurs in an npn parasitic bipolar transistor consisting of an emitter n.sup.+ region 16, a base p.sup.+ region 14, and a collector n.sup.- region with the result that a current flows between the emitter and the base is concentrated, due to the generation by a forward bias, and thus the transistor is destroyed.
To solve the above problems, a diffusion depth of the center portion of the p.sup.+ region 14 is increased, and at the same time, the n.sup.+ source region 16 is made shallower so that the area of the p.sup.+ region is enlarged, or the impurity concentration of the center portion of the p.sup.+ region is increased so that a resistivity value is lowered (Japanese Unexamined Patent Publication (Kokai) No. 60-196975). Namely, the value of the resistance in the p.sup.+ region 14 is lowered.
Therefore, to increase the diffusion depth of the center portion of the p.sup.+ region 14 and to increase the impurity concentration so as to lower the resistance R, a well shaped p.sup.+ region is formed, and impurities must be implanted at the center portion of the p.sup.+ region.
In this case, however, the impurities implanted at the center portion are diffused in the channel under the gate electrode 18, and therefore, it becomes difficult to control the impurity concentration in the channel, and thus deviations in the properties of the MOS FET are generated.